1. Field of the Invention
The present invention relates to a semiconductor device and, more particularly, to a semiconductor device having a stress testing device for applying a voltage stress, e.g., when defect screening is performed in a wafer state.
2. Description of the Related Art
When semiconductor devices are to be shipped, in order to obtain the reliability of the semiconductor devices, screening for exposing potential defects of the devices and for removing defective devices is generally performed to prevent the non-defective devices from degradation and from being defective. As a method of performing the screening, a burn-in method capable of simultaneously achieving electric field acceleration and temperature acceleration is often used. According to this burn-in method, when devices are operated at a voltage higher than a rated voltage and a temperature higher than a rated temperature, since a stress received in an initial failure period or more under rated conditions acts on the devices for a short time, devices which may cause an initial operative failure are screened in advance before the devices are shipped. Therefore, the devices which may cause an initial operative failure can be efficiently removed, and the reliability of the products can be increased.
When defective DRAMs (Dynamic Random Access Memories) are to be screened, a method of scanning word lines in an order of addresses and sequentially accessing the word lines is conventionally used. In this case, when a transfer gate transistor (cell transistor) of a memory cell having a gate connected to a word line is considered, a voltage stress is applied to the transistor in a frequency lower than that of a transistor of a peripheral circuit. For example, when a DRAM having a memory capacity of 4 Mbits is exemplified, only 4 word lines of the 4069 word lines of the DRAM are selected in one cycle, and a test for a cell transistor is completed in 1024 cycles. For this reason, the gate of the cell transistor receives a voltage stress for a 1/1024 period of the transistor of the peripheral circuit. Therefore, since a substantial period of applying a maximum electric field to the gate is short, a long time is required for screening defects.
In a DRAM used in recent years, a half (Vcc/2) of a power supply potential Vcc is generally applied to the electrode of a capacitor of a memory cell. For this reason, even when a thin film is used as the insulating film of the capacitor, since an electric field applied to the film is decreased, the reliability of the DRAM is rarely degraded. In contrast to this, since the gate oxide film of a memory cell transistor receives a potential (e.g., about 1.5.times.Vcc) boosted during selection of the cell transistor, even when the oxide film having a large thickness is used, an intensive electric field is applied to the oxide film. As a result, the reliability of the memory cell transistor is often degraded. When defective DRAMs are to be screened, especially, a cell transistor having the gate receiving a boosted potential is positively subjected to screening.
As described above, a memory cell transistor which is to be positively screened receives a voltage stress in a low frequency. In order to solve this problem, a semiconductor memory as disclosed in Published Unexamined Japanese Patent Application (Kokai) No. 3-35491 T. FURUYAMA includes a voltage stress is simultaneously applied to all word lines or word lines having a number equal to or larger than the number of word lines selected during a normal operation, thereby increasing the efficiency of applying a stress to a cell transistor.
According to this proposal, when screening of DRAMs set in a wafer state is performed using a prober and a probe card, defects are set at a level such that all defective cell transistors in each chip region are sufficiently screened, and all bit defects as major defects of a 1-M DRAM or a 4-M DRAM can be screened at a high speed. Therefore, efficiency of defect screening can be considerably increased.
The number of inputs required for a voltage stress test is preferably decreased, and it is preferable that a voltage stress can be simultaneously applied to MOS transistors of the same row (or column) in a semiconductor device having a plurality of MOS transistors arranged in a matrix form. The semiconductor device is not limited to a semiconductor memory.